1. Field of the Invention
The present invention relates to a metallic wiring board for an active matrix substrate used in an active matrix type liquid crystal display and the like and relates to a method for producing such a metallic wiring board.
2. Description of the Related Art
In recent years, a flat panel display has been earnestly studied, because it is a promising display that is thinner and lighter than a CRT (cathode ray tube) and it can be used in a personal computer or a word processor. A liquid crystal display, that is, a kind of the flat panel display, has been mainly developed recently because it is advantageous in color display since it spends little electric power and is not luminary. Especially, a liquid crystal display of an active matrix driving system using a thin film transistor (hereinafter referred to as the "TFT") is advantageous because of its quick response and a high display quality. Especially, in a TFT using amorphous silicon (hereinafter referred to as "a-Si"), a thin film can be formed at a low temperature. Therefore, such a TFT can provide a display with a large screen and a high resolution at a low cost. Accordingly, the technological development of such a TFT has been a matter of concern.
FIG. 13 is a plan view of a TFT portion in a conventional metallic wiring board. FIG. 14 is a sectional view of the TFT of FIG. 13 taken on line C--C. A source line 111 as a signal line and a gate line 104 as a scanning line are formed on an insulating glass substrate 101 longitudinally and horizontally, respectively. The TFT 100 is formed near the intersection thereof and works as a switching element of a liquid crystal display.
The metallic wiring board comprises, as is shown in FIGS. 13 and 14, the glass substrate 101 on the bottom, the gate line 104 formed on the glass substrate 101 and a first insulating film 105 formed on the gate line 104. The gate line 104 includes a little wider portion as a gate electrode 103 of the TFT 100.
The metallic wiring board further has a second insulating film 106 made from SiN.sub.x, a semiconductor layer 107 formed from a-Si on the second insulating film 106, a third insulating film 108 formed from SiN.sub.x on the center of the semiconductor layer 107, and semiconductor layers 109a and 109b made from a-Si doped with phosphorus (P). The second insulating film 106 covers the entire top surface of the glass substrate 101 bearing the gate line 104 and the first insulating film 105. The semiconductor layer 107 totally covers the gate electrode 103. The semiconductor layers 109a and 109b are formed so as to cover the semiconductor layer 107 and the edges of the third insulating film 108.
Moreover, the metallic wiring board has the source line 111 made from a metallic material such as molybdenum (Mo) and titanium (Ti) on the second insulating film 106 and a source electrode 110 branched from the source line 111. The source electrode 110 covers the whole of the semiconductor layer 109a and part of the second insulating film 106. The metallic wiring board further has a drain electrode 112 that covers the whole of the semiconductor layer 109b and part of the second insulating film 106, and a transparent pixel electrode 113 formed on the second insulating film 106 so as to be in contact with the drain electrode 112. The drain electrode 112 is made from the same material as that used for the source line 111 and the pixel electrode 113 is made from indium oxide or the like.
The production method for such a metallic wiring board is as follows:
A tantalum (Ta) film is first coated on the glass substrate 101 by a sputtering method. The Ta film is patterned to form the gate electrode 103 and the gate line 104. The first insulating film 105 is formed by anodic oxidation of the surfaces of the gate electrode 103 and the gate line 104. The first insulating film 105 and the glass substrate 101 are then coated with SiN.sub.x by a plasma CVD to form the second insulating film 106.
Next, the semiconductor layer 107 and the third insulating film 108 made from SiN.sub.x are formed in this order by the plasma CVD above the gate electrode 103 covered with the second insulating film 106. The semiconductor layers 109a and 109b are then formed so as to cover the edges of the third insulating film 108 and the whole of the semiconductor layer 107.
A metal such as Mo and Ti is coated thereon so as to cover the whole of the semiconductor layer 109a and part of the second insulating film 106 to form the source electrode 110 and the source line 111. The drain electrode 112 is formed so as to cover the whole of the semiconductor layer 109b and part of the second insulating film 106. Indium oxide or the like is then coated on the second insulating film 106 so as to come in contact with the drain electrode 112 to form the transparent pixel electrode 113. The semiconductor layers 109a and 109b are formed to provide an ohmic contact between the semiconductor layer 107 and the source electrode 110 and between the semiconductor layer 107 and the drain electrode 112.
The anodic oxidation is a method for improving the insulating property between the metallic wirings, that is, between the gate line 104 and the source line 111 and between the gate line 104 and the drain electrode 112. This method does not require complicated production steps and enables the formation of the first insulating film 105 without decreasing the yield. However, since the glass substrate 101 is subjected to a bias stress aging in the anodic oxidation process, the insulating property around the interface between the first insulating film 105 and the glass substrate 101 is degraded, causing a point defect in the liquid crystal display and degrading the quality of the displayed image. This problem is caused also in the case where a protective layer is provided on the substrate. In this case, the insulating property of the protective layer degrades during the anodic oxidation of the gate line and the gate electrode formed on the protective layer.
One of the significant elements for producing a liquid crystal display with a large screen and a high resolution is the low resistance of the metallic wiring. When the material for the metallic wiring has a low resistance, the metallic wiring can be made thin and long. As a result, pixels can be made smaller and aligned longer.
In a conventional liquid display, various kinds of metals such as Ta and Ti are used as the metallic wiring. In spite of these materials, a conventional production method limits the low resistance of a metallic film. The reason will now be described by using Ta as an example of such metallic materials.
Ta has two kinds of crystal structures: one is a tetragonal lattice and the other is a body-centered cubic lattice. The Ta having the tetragonal lattice is called .beta.-Ta, and the thin film made from .beta.-Ta has a specific resistance .rho. of 170 to 220 .mu..OMEGA.cm. The Ta having the body-centered cubic lattice is called .alpha.-Ta, and the thin film made from .alpha.-Ta has a specific resistance .rho. of 13 to 15 .mu..OMEGA.cm. Therefore, .alpha.-Ta should be formed in order to obtain a Ta film with a low resistance. Most of the Ta thin films are generally made from .beta.-Ta. In a well known method to form an .alpha.-Ta film, a small amount of nitrogen (N) is mixed in the material when forming a thin film. However, the nitrogen that has been mixed also works as an impurity, thereby limiting the low resistance of the Ta film. The Ta film formed by this method has a specific resistance of 60 to 100 .mu..OMEGA.cm.
In a liquid crystal display using a metallic wiring with a high specific resistance, when a pixel is made small in order to attain a high resolution, it is impossible to make the metallic wiring thin. As a result, the ratio of the area occupied by the metallic wiring in the whole pixel is large, thereby darkening the displayed image. Thus, the quality of the displayed image is lowered.